1. Field of the Invention
The present invention relates to reduction of power consumption by a semiconductor memory device and in particular to that by a semiconductor memory device in which a layered I/O system is installed.
2. Description of the Related Art
Recently, capacity of a semiconductor memory device is becoming larger, and wiring length in the devices is becoming longer. As a natural result, reading/writing speed to semiconductor memory devices tends to become slower. The layered I/O system is one of the techniques for improving the reading/writing speed.
According to the layered I/O system, a sub-amplifier is arranged on an I/O line connecting between a main amplifier and a sense amplifier in order to compensate the potential of the I/O line and consequently to prevent reduction of the reading/writing speed.
On the other hand, according to a conventional semiconductor memory device, other kinds of problems have occurred. Based on miniaturization of wiring in the memory device, leak current from a MOS transistor with a low threshold becomes larger. Based on increasing capacity of semiconductor memory devices, the number of elements increases, and as a result, standby current of the semiconductor memory device increases. Particularly, a semiconductor memory device with a layered I/O system includes sub-amplifiers, which cause the leak current and the standby current.
In recent years, for DRAMs, it has been more required to increase the capacitance, enhance the processing speed, and reduce the employed voltage. Moreover, the DRAMs have been applied in various new fields, e.g., field of mobile devices. Especially, it is intensively required to reduce power consumption of DRAMs.
According to a technique effective in suppressing the standby current, and thus, can cope with the above-described requirements, a substrate bias effect is applied. According to this technique, the substrate is set at a more negative potential, so that the leak current (sub-threshold current) can be reduced. However, when the potential of the substrate is decreased, the threshold voltage of the transistor increases, so that the operation speed of the transistor is reduced. Accordingly, this technique is not suitable for the case in which high-speed operation is required.
According to another technique for reducing the standby current, a sub-threshold current reduction circuit (SCRC) is used. A SCRC controls a source potential of a transistor when the transistor is on off-state, so that the bias voltage between the gate and the source of the transistor can decrease, and thus, the sub-threshold current is reduced.
Conventionally, various kinds of circuits have been proposed as the target of a SCRC for reducing a sub-threshold current; various kinds of signals are proposed for controlling a SCRC; and timings of inputting a control signal to a SCRC are proposed.
For example, according to the technique described in Japanese Unexamined Patent Publication (JP-A) No. 2000-30443 (hereinafter referred to as a cited reference 1), while switching a standby state to an active state, a SCRC is not applied to a circuit of which the operation starts at relatively early time, although the SCRC is applied to a circuit of which the operation starts at relatively early time when the circuit is in the standby state. Switching between activation and inactivation is made in response to a standby command. According to this technique, a SCRC is inapplicable to a circuit of which the operation starts at relatively early time, for example, to a sub-amplifier on a standby state.
Moreover, according to the technique described in Japanese Unexamined Patent Publication (JP-A) No. 2000-113670 (hereinafter referred to as a cited reference 2), a SCRC is applied to an X decoder while the X decoder is being switched from a standby state to an active state. In a paragraph 0012 of the cited reference 2, it is described “a hierarchic electric source control signal SCRC is activated (high or H level) prior to the activation of the row system operation”. However, it is not described in the cited reference 2 that which signal activates the signal SCRC prior to the activation of the row system operation.